ASIC Design Engineer

functionality, performance, and power targets. Implement and drive the full ASIC front‑end design flow, including lint, CDC/RDC..., flow control, and packet‑level behaviors. Proficiency with front‑end design flows, including lint, CDC/RDC, synthesis, STA...

Lugar: Irvine, CA | 20/03/2026 00:03:26 AM | Salario: S/. $151000 - 223440 per year | Empresa: Marvell