Senior ASIC Design Engineer DfT (m/f/d)

gathering and elicitation for IP Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom... in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation tools for digital designs...

Lugar: Baden-Württemberg | 07/04/2026 17:04:42 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

& Responsibilities: Requirements gathering and elicitation for IP Architecture development for CMOS IP designs Design and RTL coding... methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard...

Lugar: Baden-Württemberg | 07/04/2026 17:04:34 PM | Salario: S/. No Especificado | Empresa: Advantest

Software Engineer (w/m/d) - TV

. Extra Loot: Zuschüsse für Deutschlandticket & JobRad, Urban Sports Club, RTL+ Premium, Corporate Benefits, Team-Events... About the Company smartclip is the adtech development unit of RTL Group — Europe’s leading free-to-air broadcaster group...

Lugar: Berlin | 06/04/2026 17:04:09 PM | Salario: S/. No Especificado | Empresa: Instaffo

FPGA Design Engineer (m/f/d)

families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...

Lugar: Berlin | 03/04/2026 21:04:22 PM | Salario: S/. No Especificado | Empresa: GE Vernova

DevOps Engineer (w/m/d) - Google Cloud Platform

-Entwicklungseinheit der RTL Group – Europas führender Free-TV Sendergruppe. Unsere proprietäre Werbetechnologie ist auf die spezifischen.... Die Media Sales Division von smartclip wird mit RTL AdConnect und G&J iMS zu einem internationalen Advertising Sales Champion...

Lugar: Hamburg | 03/04/2026 17:04:33 PM | Salario: S/. No Especificado | Empresa: Smartclip

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 03/04/2026 02:04:46 AM | Salario: S/. No Especificado | Empresa: Advantest