Junior Digital Circuit Designer

www.gf.com. Your Job Design and implement digital logic blocks (RTL) using Verilog/SystemVerilog. Integrate digital.... Analyze design behavior and resolve RTL issues. Support synthesis, timing analysis, and implementation tasks. Participate...

Lugar: Dresden, Sachsen | 24/01/2026 22:01:49 PM | Salario: S/. No Especificado | Empresa: GlobalFoundries

FPGA Design Engineer (m/f/d)

families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...

Lugar: Berlin | 17/01/2026 03:01:16 AM | Salario: S/. No Especificado | Empresa: GE Vernova

ASIC Digital Backend Engineer (m/f/d)

. Job Description As digital backend engineer (m/f/diverse) for Continental ASIC you generate digital block layouts from digital RTL code, choosing... specifications and RTL design Creating design implementation constraints Performing RTL synthesis including DFT insertion...

Lugar: Frankfurt am Main, Hessen | 16/01/2026 18:01:40 PM | Salario: S/. No Especificado | Empresa: Aumovio