Digital Verification Engineer

. Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench... and organizational skills Strong process-oriented mindset. Expert-level System Verilog Programming Advanced UVM/SV (Universal...

Lugar: Tijuana, B.C. | 28/05/2026 00:05:16 AM | Salario: S/. No Especificado | Empresa: NAPS

SoC/IP Design Verification Engineer

. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage..., and signoff. Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models...

Lugar: Guadalajara, Jal. | 02/04/2026 17:04:58 PM | Salario: S/. No Especificado | Empresa: Intel
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