Position Title: FPGA/ASIC Engineer Position Description: Protingent Staffing has an exciting contract opportunity located in Northridge, CA. Job Responsibilities: Architecture & Design: Architect and implement high-performance FPGA/AS...
Duration- 12 Months Contract Must Have Skills: - Work Autonomously - Creating and maintaining Version Control & Repository Management - Understanding for ASIC EDA & Debug tools/workflows - Creating and maintaining CI/CD workflows - M...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Description: Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high...
Duration: 6 months Job Duties: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and Client internal IPs. Successful candidates will be responsible for leading, and participating in,...