Senior RTL Verification Engineer

Position Title: Senior RTL Verification Engineer Position Description: Protingent Staffing has an exciting RTL... endpoint and reader chip designs including C behavioral model development, RTL model coding, debug, verification coverage...

Lugar: Seattle, WA | 15/11/2025 18:11:29 PM | Salario: S/. No Especificado | Empresa: Protingent

Front-End Infrastructure Engineer

-quality support for verification processes. RTL Architecture Tool Deployment & Support: You will successfully deploy... and maintain tools for RTL Architecture, ensuring integration with FE verification flows and addressing any support requirements...

Lugar: Austin, TX | 12/12/2025 18:12:22 PM | Salario: S/. No Especificado | Empresa: Protingent

Hardware Developer Engineer Intern

process, such as: Logic (RTL) design and verification, physical design, and analog/IO design Electronic design...

Lugar: USA | 12/12/2025 18:12:41 PM | Salario: S/. No Especificado | Empresa: IBM

Hardware Developer Intern 2026

process, such as: Logic (RTL) design and verification, physical design, and analog/IO design Electronic design automation... following technology areas: Microprocessor/ASIC Design Skills: VHDL, Verilog, RTL, SPICE, TCL, UVM, verification, and testing...

Lugar: Texas - Minnesota | 11/12/2025 18:12:16 PM | Salario: S/. No Especificado | Empresa: IBM

Principal FPGA Engineer

that specializes on the power convertors (MV, UV, Space) Minimum Qualifications: · Ideally 10+ years of FPGA/RTL design...

Lugar: Sterling, VA | 05/12/2025 21:12:05 PM | Salario: S/. No Especificado | Empresa: Actalent

Principal FPGA Engineer

/RTL design and verification experience with flight or high-reliability systems. · Bachelor’s degree in electrical...

Lugar: Sterling, VA | 04/12/2025 23:12:45 PM | Salario: S/. No Especificado | Empresa: Actalent

Design Engineer IV

: Skills-"PCB LAYOUT", "RTL", “FPGA” 8 years of end-to-end FPGA design experience (RTL, Simulation, Implementation, Hands...

Lugar: Sunnyvale, CA | 27/11/2025 18:11:15 PM | Salario: S/. No Especificado | Empresa: Pyramid Consulting

Core Engineering - Design Engineer V

-to-Day Responsibilities Perform PPA optimization with Fusion compiler Conduct RTL and netlist level power analysis... Setup, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing) Implement some blocks at RTL and UPF...

Lugar: Sunnyvale, CA | 19/11/2025 03:11:55 AM | Salario: S/. No Especificado | Empresa: Artech Information Systems