Job Title: Senior RTL Design Engineer Position Description: Protingent Staffing has an exciting contract Senior RTL... including Ethernet, PCIe, and DDR • Applies RTL implementation techniques to qualify the design to meet required power...
in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute... Design. Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging...
Immediate need for a talented RTL Design Engineer .This is a 06-12+ Months contract opportunity with long-term...
record of successful tape-outs and silicon bring-up (ASIC/FPGA). Expert-level proficiency in Verilog/SystemVerilog RTL...
: Collaborate with RTL Designers, System Architects to define verification specifications. Design the test suites for full chip... and block level verification, develop direct and constrained random testcases, analyze and debug simulations at RTL and Gate...
Responsibilities Perform PPA optimization with Fusion compiler Conduct RTL and netlist level power analysis Execute post-processing... reports of ASIC flows (Synthesis, PD, Power, Timing) Implement some blocks at RTL and UPF Document and communicate findings...
, CA. Job Responsibilities: Collaborate with RTL Designers, System Architects to define verification specifications. Design the test suites... at RTL and Gate level. Build the functional coverage models, collect and analyze coverage data. Build test benches for Low...
through RTL implementation, verification, and system-level integration across multiple FPGA platforms. Define, document... in and lead design reviews. Develop high-quality, reusable RTL and verification environments, including self-checking testbenches...
at various design stages, spanning from RTL to GDSII. Contribute to the development, improvement, and automation of various.... Investigate and address power inefficiencies, providing actionable feedback to the RTL design team. Minimum Qualifications...
, developing, optimizing, and maintaining FPGA RTL using Verilog/SystemVerilog and/or VHDL Supporting the full FPGA development...