System IP / RTL Design Engineer

Job Title: System IP/RTL Design Engineer Position Description: Protingent Staffing has an exciting contract System IP... / RTL Design Engineer opportunity with our client located in Austin, TX. Job Responsibilities: Work on RTL design...

Lugar: Texas | 14/01/2026 18:01:46 PM | Salario: S/. No Especificado | Empresa: Protingent

RTL Design Engineer

Immediate need for a talented RTL Design Engineer .This is a 06-12+ Months contract opportunity with long-term...

Lugar: Dallas, TX | 06/01/2026 18:01:34 PM | Salario: S/. $58 - 60 per hour | Empresa: Pyramid Consulting

Sr & Principal FPGA

of 10-15 years of FPGA/RTL design and verification experience with flight or high-reliability systems. Bachelor’s degree...

Lugar: Sterling, VA | 21/01/2026 20:01:13 PM | Salario: S/. No Especificado | Empresa: Actalent

Sr & Principal FPGA

of 10-15 years of FPGA/RTL design and verification experience with flight or high-reliability systems. Bachelor’s degree...

Lugar: Sterling, VA | 21/01/2026 03:01:29 AM | Salario: S/. No Especificado | Empresa: Actalent

Senior FPGA Engineer

of 10-15 years of FPGA/RTL design and verification experience with flight or high-reliability systems. Bachelor’s degree...

Lugar: Sterling, VA | 18/01/2026 01:01:58 AM | Salario: S/. No Especificado | Empresa: Actalent

Sr & Principal FPGA

of 10-15 years of FPGA/RTL design and verification experience with flight or high-reliability systems. Bachelor’s degree...

Lugar: Sterling, VA | 17/01/2026 22:01:58 PM | Salario: S/. No Especificado | Empresa: Actalent

Front-End Infrastructure Engineer

, maintaining an open line of communication to ensure high-quality support for verification processes. RTL Architecture Tool... Deployment & Support: You will successfully deploy and maintain tools for RTL Architecture, ensuring integration with FE...

Lugar: Austin, TX | 14/01/2026 18:01:57 PM | Salario: S/. No Especificado | Empresa: Saige Partners

Hardware Design Engineer 5

within the last 3 years. Advanced knowledge of UVM and System Verilog programming languages. Basic knowledge of Verilog RTL...

Lugar: Redmond, WA | 11/01/2026 02:01:58 AM | Salario: S/. No Especificado | Empresa: Actalent

FPGA Engineer

. Expertise in RTL optimized design technique in digital and DSP domain with Verilog/SystemVerilog and/or VHDL. Proficient...

Lugar: Plano, TX | 10/01/2026 19:01:24 PM | Salario: S/. $48 - 58 per hour | Empresa: Actalent