Senior RTL Design Engineer

Job Title: Senior RTL Design Engineer Position Description: Protingent Staffing has an exciting contract Senior RTL... including Ethernet, PCIe, and DDR • Applies RTL implementation techniques to qualify the design to meet required power...

Lugar: Folsom, CA | 11/03/2026 18:03:27 PM | Salario: S/. No Especificado | Empresa: Protingent

ASIC/RTL Design Engineer

in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute... Design. Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging...

Lugar: Santa Clara, CA | 23/01/2026 00:01:31 AM | Salario: S/. No Especificado | Empresa: US Tech Solutions

RTL Design Engineer

Immediate need for a talented RTL Design Engineer .This is a 06-12+ Months contract opportunity with long-term...

Lugar: Dallas, TX | 06/01/2026 18:01:20 PM | Salario: S/. $58 - 60 per hour | Empresa: Pyramid Consulting

FPGA Design Engineer

, developing, and supporting FPGA-based solutions for advanced robotic and medical systems. The engineer will own RTL design.... Responsibilities: Key responsibilities include, but are not limited to: Designing, developing, optimizing, and maintaining FPGA RTL...

Lugar: Santa Clara, CA | 13/03/2026 23:03:03 PM | Salario: S/. No Especificado | Empresa: US Tech Solutions

FPGA/ASIC Design Engineer

record of successful tape-outs and silicon bring-up (ASIC/FPGA). Expert-level proficiency in Verilog/SystemVerilog RTL...

Lugar: Northridge, CA | 11/03/2026 18:03:11 PM | Salario: S/. No Especificado | Empresa: Protingent

Senior Staff Engineer, Digital Verification - ACAS

: Collaborate with RTL Designers, System Architects to define verification specifications. Design the test suites for full chip... and block level verification, develop direct and constrained random testcases, analyze and debug simulations at RTL and Gate...

Lugar: San Jose, CA | 10/03/2026 18:03:59 PM | Salario: S/. No Especificado | Empresa: Protingent

Core Engineering - Design Engineer V

Responsibilities Perform PPA optimization with Fusion compiler Conduct RTL and netlist level power analysis Execute post-processing... reports of ASIC flows (Synthesis, PD, Power, Timing) Implement some blocks at RTL and UPF Document and communicate findings...

Lugar: Sunnyvale, CA | 06/03/2026 21:03:46 PM | Salario: S/. No Especificado | Empresa: Artech Information Systems

Senior Staff Engineer, Digital Verification - ACAS

, CA. Job Responsibilities: Collaborate with RTL Designers, System Architects to define verification specifications. Design the test suites... at RTL and Gate level. Build the functional coverage models, collect and analyze coverage data. Build test benches for Low...

Lugar: San Jose, CA | 03/03/2026 18:03:48 PM | Salario: S/. No Especificado | Empresa: Protingent