), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero... flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family...
, such as Cadence Genus, Innovius, Conformal, Tempus, Voltus, or Synopsys Design Compiler, IC Compiler, Fusion Compiler, PrimeTime...
Design and Signoff tools, such as Cadence Genus, Innovius, Tempus, Voltus, or Synopsys Design Compiler, IC Compiler, Fusion...
characterization is a plus. Experience with Synopsys TCAD tools and Cadence Virtuoso a plus. Position requires very strong analytical...
with scripting, installing and managing EDA tools (Cadence, Mentor, Synopsys), and supporting IC design engineers by maintaining...
Lugar:
Irvine, CA | 23/03/2026 02:03:17 AM | Salario: S/. $145000 - 190000 per year | Empresa:
MaxLinear with scripting, installing and managing EDA tools (Cadence, Mentor, Synopsys), and supporting IC design engineers by maintaining...
Lugar:
Irvine, CA | 21/03/2026 21:03:17 PM | Salario: S/. $145000 - 190000 per year | Empresa:
MaxLinear constraints for complex SoC designs. Expertise in Static Timing Analysis (STA) using tools such as Synopsys PrimeTime or Cadence... structures and recommend timing-driven micro-architectural improvements. Expertise with constraint analysis tools (Synopsys TCM...
), synthesis (e.g., Synopsys Synplify), FPGA tools (e.g., Vivado). – Experience in synthesis and static timing analysis, knowledge..., PSK, QAM, OFDMA, PCIe, Ethernet, AMBA, DDR, UVM, Questa, Spyglass, Synopsys, Synplify, Vivado, ASIC, Electrical Engineer...
implementations, coverage analysis, and more. Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation...
. – Experience in EDA tools such as simulators (e.g., Questa), lint checkers (e.g., Spyglass) synthesis (e.g., Synopsys Synplify..., PCIe, Ethernet, AMBA, DDR, UVM, Questa, Spyglass, Synopsys, Synplify, Vivado, ASIC, Electrical Engineer, Maryland...