Job Function: ASIC Physical Design implementation using IC Compiler;Logic Synthesis, I/O Pad Ring Design, Floor Planning, Placement, CTS, Routing, STA with Timing Closure in Advanced Technology Nodes.Timing closure methodology implementa...
Essential Duties and Responsibilities: : Planning the verification of complex digital systems Creating a constrained-random verification environment using System Verilog and UVM Identifying and writing all types of coverage measures for...
Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. A...
Sr ASIC/RTL Design Engineer (NoC / Ethernet / PCIe / UCIe) - Remote Location: Remote - Anywhere in US / Canada Full-time: Salary + Benefits + Bonuses / Contractor Work Status: Must be US citizen or Lawful Permanent Resident. Responsibil...
Sr ASIC/RTL Design Engineer (NoC / Ethernet / PCIe / UCIe) - Remote Location: Remote - Anywhere in US / Canada Full-time: Salary + Benefits + Bonuses / Contractor Work Status: Must be US citizen or Lawful Permanent Resident. Responsibil...
FPGA/ASIC Verification Engineer - 31975 Direct Hire Salary Plus Benefits Locations: Columbia, MD or Rochester NY US Citizenship required Onsite Perform FPGA design verification and validation of embedded electronic communication. A...
ROLE OVERVIEW: A leading technology organization is seeking an FPGA / ASIC Verification Engineer to support the development of secure, next-generation communication systems used in mission-critical environments. This role focuses on ver...
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re ...
Lugar:
Atlanta, GA | 29/03/2026 03:03:19 AM | Salario: S/. $119900 - 191500 per year | Empresa:
CienaJob Description: Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for...
Lugar:
San Jose, CA | 29/03/2026 01:03:15 AM | Salario: S/. No Especificado | Empresa:
CyientOur Mission At Palo Alto Networks®, we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. H...