Senior Software Engineering Manager

for device design, chip fabrication workflows, physics-informed data analysis, quantum gate-design, and quantum mitigation... with you when the right role opens up in the future! Export Licensing Compliance Rigetti is committed to full compliance...

Lugar: Berkeley, CA - Fremont, CA | 17/06/2026 01:06:26 AM | Salario: S/. $220000 - 250000 per year | Empresa: Rigetti

Principal Engineer, Digital IC Design

-defect product. Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality.... This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the...

Lugar: Santa Clara, CA | 11/06/2026 20:06:37 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Design Verification Engineer

of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data.... This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the...

Lugar: Santa Clara, CA | 23/05/2026 00:05:26 AM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Verification Engineer

of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations · Coach..., understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level...

Lugar: Santa Clara, CA | 22/04/2026 01:04:29 AM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Technical Lead, Design Verification

with gate-level simulation and post-silicon validation debug Experience mentoring junior verification engineers Education... process. This position may require access to technology and/or software subject to U.S. export control laws and regulations...

Lugar: Santa Clara, CA | 07/04/2026 21:04:34 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Design Verification Engineer

with Post-Silicon validation and debug. Experience with Gate Level Simulations. Excellent communication skills to interface.... This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the...

Lugar: Morrisville, NC | 01/05/2026 18:05:11 PM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Principal Digital Design Engineer

experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional.... This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the...

Lugar: San Diego, CA | 30/04/2026 23:04:44 PM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Lead Quantum Device Theorist

to improve qubit readout fidelity and quantum gate performance across our R&D platforms. This role demands strong cross...-functional collaboration with specialists in qubit readout, gate calibration, control systems, and superconducting circuit design...

Lugar: Berkeley, CA - Fremont, CA | 26/03/2026 22:03:44 PM | Salario: S/. $195000 - 225000 per year | Empresa: Rigetti

Senior Staff Engineer, Digital IC Design

both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip.... This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the...

Lugar: Westborough, MA | 11/06/2026 21:06:08 PM | Salario: S/. $151000 - 223440 per year | Empresa: Marvell

Senior Staff Engineer, Digital IC Design

both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip.... This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the...

Lugar: Westborough, MA | 10/06/2026 20:06:13 PM | Salario: S/. $151000 - 223440 per year | Empresa: Marvell