Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles

such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis Experience.../gate level simulation, synthesis, place and route, static timing analysis, and power analysis Experience with translating...

Lugar: Virginia | 20/03/2026 18:03:10 PM | Salario: S/. $114000 - 171000 per year | Empresa: Northrop Grumman

Electronics Engineer Sr

circuit design in areas such as analog, digital, microcontroller, Field Programmable Gate Arrays (FPGAs), and/or power supply...

Lugar: Littleton, CO | 21/03/2026 00:03:12 AM | Salario: S/. $98300 - 170315 per year | Empresa: Lockheed Martin

Global Engineering Director

management standards (Stage-Gate / NPI governance) consistent with AMETEK Corporate requirements. Monitor key KPIs: schedule.... Project & Portfolio Management Mastery of project governance (Stage-Gate/NPI), planning, budgeting, and resource...

Lugar: Madison, WI | 12/03/2026 18:03:42 PM | Salario: S/. $170000 per year | Empresa: AMETEK

Staff Project Manager Engineer

experience managing distributed and multicultural teams. Competencies Must Have In-depth understanding of Toll Gate... / Stage Gate product development processes. Strong experience in project management strategy and execution. Extensive...

Lugar: Austin, TX | 03/01/2026 18:01:02 PM | Salario: S/. $150000 - 170000 per year | Empresa: WhiteCrow Research

Site Manager

results CAPEX Work closely with the Engineering group to execute the annual capital plan, utilizing the stage gate...

Lugar: Joliet, IL | 11/03/2026 18:03:27 PM | Salario: S/. $145000 - 170000 per year | Empresa: PQ

Site Manager

results CAPEX Work closely with the Engineering group to execute the annual capital plan, utilizing the stage gate...

Lugar: Joliet, IL | 11/03/2026 00:03:50 AM | Salario: S/. $145000 - 170000 per year | Empresa: PQ Corporation

New College Grad - Design Engineer

Perform RTL, synthesized netlist, gate‑level, and post‑layout develop verification at block, subsystem, and full‑chip levels... specifications, and logic diagrams Experience with RTL design, Verilog verification, and gate‑level simulation Knowledge of design...

Lugar: San Jose, CA | 22/03/2026 01:03:30 AM | Salario: S/. $80000 - 170000 per year | Empresa: Micron