Business Strategy Manager

, participates in gate reviews and identification of key personnel requirements within the proposal. Performs duties as the...

Lugar: San Diego, CA | 08/02/2026 03:02:33 AM | Salario: S/. $145000 - 250000 per year | Empresa: Alutiiq

Principal Digital IC Design Engineer

of digital IC circuit design in an HDL synthesis environment Ability to develop RTL code and understand how RTL will map to gate...

Lugar: Austin, TX | 18/03/2026 18:03:18 PM | Salario: S/. $129400 - 247800 per year | Empresa: Skyworks

Staff Design Engineer

and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification.... Proven track record to meet performance, area, and power targets. Experience with RTL and gate-level verification processes...

Lugar: San Jose, CA | 25/03/2026 21:03:41 PM | Salario: S/. $116000 - 246000 per year | Empresa: Micron

Principal Engineer, Verification

designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations..., understanding of methodology (object-oriented programming, white-box/black-box, directed/random testing, coverage, gate-level...

Lugar: Santa Clara, CA | 10/03/2026 19:03:07 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell