Lead ASIC Design Engineer
: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static...
Lugar: San Jose, CA | 21/06/2026 01:06:58 AM | Salario: S/. No Especificado | Empresa: Broadcom
Infra Systems Physical Architect
Sync Clock Routing Formal verification experience Power domain analysis experience Design Compiler/Fusion Compiler/Genus...
Lugar: San Diego, CA | 20/06/2026 02:06:49 AM | Salario: S/. No Especificado | Empresa: Qualcomm
GOLF COURSE SUPERINTENDENT NF4
¿ in its message. Ensures the attractiveness and constant readiness for play of the course. Determines the appropriate genus...
Lugar: Oceanside, CA | 19/06/2026 19:06:06 PM | Salario: S/. $34 - 37 per hour | Empresa: Federal government of the United States
Principal Product Engineer, Synthesis
products. Job responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis..., Performance & Area (PPA) for latest digital ASICs Understand the internal flow within the Genus for newly developed features...
Lugar: San Jose, CA | 17/06/2026 01:06:45 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
RTL2GDS, Principal AE
, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus...
Lugar: San Jose, CA | 13/06/2026 23:06:02 PM | Salario: S/. $123200 - 228800 per year | Empresa: Cadence Design Systems
Senior Implementation Methodology Engineer
-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus). Prior experience in data...
Lugar: Santa Clara, CA | 13/06/2026 21:06:44 PM | Salario: S/. No Especificado | Empresa: Nvidia
FPGA Engineer Engineer (eInfochips)
, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock...
Lugar: San Jose, CA | 13/06/2026 18:06:05 PM | Salario: S/. No Especificado | Empresa: Arrow Electronics
RTL2 GDS, Sr Principal AE
, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus...
Lugar: Estados Unidos | 13/06/2026 02:06:56 AM | Salario: S/. $126000 - 234000 per year | Empresa: Cadence Design Systems
Principal Engineer, Digital Design Engineer (AI/ML)
(Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal) Lead architecture and design reviews..., BIST), and clock domain crossing methodologies Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal...
Lugar: Chandler, AZ | 12/06/2026 19:06:35 PM | Salario: S/. No Especificado | Empresa: Analog Devices
Senior ASIC CAD Engineer
production experience running standard industry tools like Synopsys Design Compiler/PrimeTime or Cadence Genus/Tempus. Expert...
Lugar: Santa Clara, CA | 09/06/2026 18:06:55 PM | Salario: S/. No Especificado | Empresa: Palo Alto Networks