Staff Design Engineer

and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification... at block, subsystem, and full chip level Facilitate netlist bring up to achieve basic functionality Responsible...

Lugar: San Jose, CA | 25/03/2026 23:03:45 PM | Salario: S/. $116000 - 246000 per year | Empresa: Micron

ASIC Design Engineer: DFT-IP

development for AMS IP Simulation/Verification of ATE test suite at IP, Block, and Top-level netlist Collaborate with global CAD...

Lugar: Morrisville, NC | 05/03/2026 22:03:07 PM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Package Design Engineer

. Netlist management for heterogeneous chiplet assemblies using latest EDA solutions. Supporting activities related... packaging, chiplet architectures – co-design, layout, and netlist management. Knowledge of Signal and Power Integrity...

Lugar: Santa Clara, CA | 27/03/2026 21:03:39 PM | Salario: S/. $158600 - 234650 per year | Empresa: Marvell

Senior Design Engineer

best known design and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate... level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve basic functionality...

Lugar: San Jose, CA | 21/03/2026 19:03:37 PM | Salario: S/. $93000 - 198000 per year | Empresa: Micron

Design Engineer

in 2nm/3nm/5nm technology nodes . The person should have hands on experience on netlist- gds implementation of multimillion...

Lugar: San Jose, CA | 25/03/2026 20:03:05 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Staff DFT Engineer

from RTL/netlist through post-silicon debug. In this role, you will partner closely with RTL, Physical Design, and ATE teams... DFT lifecycle experience, from RTL/netlist through silicon debug Strong debugging skills, attention to detail, and sense...

Lugar: Santa Clara, CA | 25/02/2026 02:02:50 AM | Salario: S/. $128000 - 189370 per year | Empresa: Marvell

Physical Design Engineer

role in the backend implementation flow — from RTL/netlist through GDSII/tape-out for FPGA/SoC devices...), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII. Apply PPA optimization...

Lugar: San Jose, CA | 25/02/2026 22:02:38 PM | Salario: S/. $127400 - 184400 per year | Empresa: Altera