Design Engineer

in 2nm/3nm/5nm technology nodes . The person should have hands on experience on netlist- gds implementation of multimillion...

Lugar: San Jose, CA | 25/03/2026 20:03:05 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Digital Design Engineer

and effective chip layout. Convert RTL code into a gate-level netlist, ensuring the design meets area, power, and performance...

Lugar: Pasadena, CA | 24/03/2026 21:03:53 PM | Salario: S/. $100000 per year | Empresa: AMETEK

Senior Design Engineer

best known design and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate... level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve basic functionality...

Lugar: San Jose, CA | 21/03/2026 19:03:37 PM | Salario: S/. $93000 - 198000 per year | Empresa: Micron

Design Engineer

such as Python, Tcl, and SystemVerilog. Responsibilities: Perform PPA optimization with Fusion compiler. Conduct RTL and netlist...

Lugar: Sunnyvale, CA | 21/03/2026 18:03:24 PM | Salario: S/. No Especificado | Empresa: Aditi Consulting

ASIC Power Engineer

with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files... the design, reading the vector, and performing a quality check? Read_library Read_verilog/netlist Read_spef Read_sdc...

Lugar: Alpharetta, GA | 13/03/2026 03:03:47 AM | Salario: S/. No Especificado | Empresa: Diverse Lynx