Human Resources Assistant
Human Resources Assistant Company Overview: Netlist Inc. (NASDAQ: NLST) is a leading provider of high-performance...
Lugar: Irvine, CA | 24/03/2026 18:03:34 PM | Salario: S/. $25 - 30 per hour | Empresa: Netlist
Architecture/Design/Development - Application Architect III
compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format...
Lugar: Estados Unidos | 31/03/2026 17:03:50 PM | Salario: S/. No Especificado | Empresa: V R Della Infotech
ASIC Digital Backend Physical Implementation Engineer
, and maintain a robust flow from netlist to full closure and GDSII generation. Partner with RTL circuit designers and other layout...
Lugar: Atlanta, GA | 28/03/2026 20:03:47 PM | Salario: S/. $119900 - 191500 per year | Empresa: Ciena
ASIC Physical Design Engineer
Perform PPA optimization with Fusion compiler to enhance ASIC efficiency. Conduct RTL and netlist level power analysis...
Lugar: San Francisco, CA | 28/03/2026 18:03:04 PM | Salario: S/. No Especificado | Empresa: Mercor
Package Design Engineer
. Netlist management for heterogeneous chiplet assemblies using latest EDA solutions. Supporting activities related... packaging, chiplet architectures – co-design, layout, and netlist management. Knowledge of Signal and Power Integrity...
Lugar: Santa Clara, CA | 27/03/2026 21:03:39 PM | Salario: S/. $158600 - 234650 per year | Empresa: Marvell
Design Engineer V - Power ASIC Engineer
optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report...
Lugar: Sunnyvale, CA | 27/03/2026 18:03:05 PM | Salario: S/. No Especificado | Empresa: Pyramid Consulting
Calibre Product Engineer – Advanced
. Position requires experience in the following: 1. Working with Layout Versus Schematics (LVS) 2. Working with Spice netlist...
Lugar: Wilsonville, OR | 27/03/2026 03:03:12 AM | Salario: S/. $127462 - 197700 per year | Empresa: Siemens
ASIC Power Engineer
are Python, tcl and SystemVerilog. Responsibilities Perform PPA optimization with Fusion compiler. Perform RTL and netlist...
Lugar: Sunnyvale, CA | 27/03/2026 02:03:28 AM | Salario: S/. No Especificado | Empresa: US Tech Solutions
HBM SoC Physical Design Engineer
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers... from netlist to GDSII on advanced nodes and complex designs. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus...
Lugar: Richardson, TX | 25/03/2026 23:03:44 PM | Salario: S/. No Especificado | Empresa: Micron
Staff Design Engineer
and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification... at block, subsystem, and full chip level Facilitate netlist bring up to achieve basic functionality Responsible...
Lugar: San Jose, CA | 25/03/2026 23:03:45 PM | Salario: S/. $116000 - 246000 per year | Empresa: Micron