Senior Electrical Engineer- FPGA Development

lifecycle, from concept to production. It takes experts in system architecture definition, RTL design, synthesis, timing.../System Verilog and hardware description language (HDL) coding practices Proficiency in design, register-transfer level (RTL...

Lugar: Round Rock, TX | 01/04/2026 21:04:08 PM | Salario: S/. No Especificado | Empresa: Dell

ASIC Design Engineer

documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets.... Crafting micro-architecture, implementing them in RTL, and delivering fully verified, synthesis/timing clean builds...

Lugar: Santa Clara, CA | 01/04/2026 19:04:24 PM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia