Senior Principal Digital Design Engineer

compression, AI/HW accelerators) Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL Work... partitioning, and execution plan Lead improvements to design methodology to maximize efficiency and predictability RTL...

Lugar: Carlsbad, CA | 28/06/2026 22:06:30 PM | Salario: S/. $186000 - 228000 per year | Empresa: MaxLinear

SoC Logic Design Engineer

semiconductor industry. Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL) coding... verification plans to confirm design features are thoroughly verified and address any RTL test failures with corrective measures...

Lugar: Hillsboro, OR | 28/06/2026 22:06:10 PM | Salario: S/. No Especificado | Empresa: Intel

GPU Design Verification Engineer

environment, root cause issues, and implement corrective measures. Collaborate with architects, RTL developers, and physical... for design enhancements and code design changes in RTL while adhering to coding guidelines. Analyze timing reports to optimize...

Lugar: Folsom, CA | 28/06/2026 20:06:12 PM | Salario: S/. No Especificado | Empresa: Intel

Product Development Engineer

pattern simulation and validation to ensure test effectiveness prior to tape-out. Collaborate with RTL, DFT, and Design..., test compression, IJTAG and JTAG networks Experience with RTL design, synthesis, and verification flows. Experience...

Lugar: San Jose, CA | 28/06/2026 18:06:15 PM | Salario: S/. $106200 - 153675 per year | Empresa: Altera

Design Verification Engineer

approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design... with RTL designers to resolve issues. Implement and maintain functional coverage, code coverage, assertion coverage...

Lugar: Plano, TX | 28/06/2026 17:06:31 PM | Salario: S/. No Especificado | Empresa: Purple Hires Inc

Lead ASIC DFT (Design-for-Test) Engineer - Remote

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: Estados Unidos | 28/06/2026 17:06:28 PM | Salario: S/. No Especificado | Empresa: Saransh Inc