CPU Performance Modeling Engineer (Multiple Levels)

and compiler technology a plus Collaborate with CPU Performance Architecture and RTL team members to identify opportunities... performance model Work with RTL and design team to assess implementation cost for new features Collaborate with performance...

Lugar: Austin, TX | 03/03/2026 03:03:52 AM | Salario: S/. $148300 - 222500 per year | Empresa: Qualcomm

Design Verification Lead

with architects and RTL designers to assess the impact of architectural changes. Create, develop, and maintain UVM/SystemVerilog...

Lugar: Santa Clara, CA | 26/02/2026 00:02:57 AM | Salario: S/. $86900 - 203800 per year | Empresa: Capgemini

Senior Emulation Engineer

, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification, and firmware teams.... - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize...

Lugar: Santa Clara, CA | 17/03/2026 21:03:58 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities.... Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge and hands-on experience with synthesis and STA methodologies...

Lugar: Irvine, CA | 17/04/2026 02:04:38 AM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Senior Staff Digital Design Engineer

blocks.  Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL that meets... ASIC design, including micro‑architecture development, RTL implementation (SystemVerilog preferred), and integration...

Lugar: Irvine, CA | 20/03/2026 03:03:41 AM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell