and compiler technology a plus Collaborate with CPU Performance Architecture and RTL team members to identify opportunities... performance model Work with RTL and design team to assess implementation cost for new features Collaborate with performance...
Lugar:
Austin, TX | 03/03/2026 03:03:52 AM | Salario: S/. $148300 - 222500 per year | Empresa:
Qualcomm Summary: As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level and top...
Lugar:
Austin, TX | 03/03/2026 03:03:30 AM | Salario: S/. $148300 - 222500 per year | Empresa:
Qualcomm. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation...
mitigation, and design optimization. Drive cross‑functional collaboration with architecture, RTL, PHY, SI/PI, firmware, system...
with architects and RTL designers to assess the impact of architectural changes. Create, develop, and maintain UVM/SystemVerilog...
, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification, and firmware teams.... - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize...
. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities.... Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge and hands-on experience with synthesis and STA methodologies...
Lugar:
Irvine, CA | 17/04/2026 02:04:38 AM | Salario: S/. $135900 - 201130 per year | Empresa:
Marvell timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the..., from RTL to GDSII. Knowledge and hands-on experience with sta methodologies and implementation. Proficiency in using STA...
Lugar:
Irvine, CA | 16/04/2026 23:04:48 PM | Salario: S/. $135900 - 201130 per year | Empresa:
Marvell blocks.  Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL that meets... ASIC design, including micro‑architecture development, RTL implementation (SystemVerilog preferred), and integration...
Lugar:
Irvine, CA | 20/03/2026 03:03:41 AM | Salario: S/. $135900 - 201130 per year | Empresa:
Marvell, including phase noise, jitter analysis, budgeting, and feedback loop dynamics. Proficiency in designing/debugging RTL...
Lugar:
Dallas, TX | 08/04/2026 21:04:08 PM | Salario: S/. $190000 - 200000 per year | Empresa:
Actalent