RTL Design Tech Lead (ASIC/SoC)

, adaptability, and selfless collaboration in pursuit of ambitious technical goals. The team is seeking an experienced RTL Design... Tech Lead to drive microarchitecture, RTL development, and technical execution across complex ASIC/SoC programs...

Lugar: Santa Clara County, CA | 14/05/2026 23:05:41 PM | Salario: S/. $220000 - 250000 per year | Empresa: MRL Consulting Group

Engineering Director - Verification IP

Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters... field from reputed institute · 18+ years of working experience in RTL design, IP/VIP development/verification or emulation...

Lugar: Austin, TX | 02/06/2026 22:06:48 PM | Salario: S/. $180400 - 250000 per year | Empresa: Siemens

Design Verification (DV) Engineer

flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers... Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage...

Lugar: Estados Unidos | 30/04/2026 23:04:18 PM | Salario: S/. $175000 - 250000 per year | Empresa: Hudson River Trading

Principal DSP Engineer

and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research...

Lugar: Santa Clara, CA | 23/06/2026 23:06:25 PM | Salario: S/. $166520 - 249500 per year | Empresa: Marvell

Staff Design Engineer

architecture specifications for new features. Support the creation of schematics and/or RTL blocks Define best known design... and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification...

Lugar: San Jose, CA | 20/05/2026 19:05:18 PM | Salario: S/. $145000 - 246000 per year | Empresa: Micron

Principal Engineer, Digital IC Design

, or related fields with 5-10 years of experience. Proven experience in taping out complex SoCs and post silicon debug Strong RTL..., and timing constraints. Understanding of how front-end RTL decisions impact physical implementation and verification...

Lugar: Santa Clara, CA | 11/06/2026 18:06:23 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Physical Design/Implementation Engineer

flows for Complex SubSystems Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floor... team Work with DFT team and SOC team for DFT insertion and closing timing at SOC level Work with RTL team to close...

Lugar: Santa Clara, CA | 09/05/2026 17:05:45 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Prinicipal Emulation Engineer

, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification... environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions...

Lugar: Santa Clara, CA | 05/05/2026 21:05:21 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Emulation Engineer

, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification... environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions...

Lugar: Santa Clara, CA | 05/05/2026 17:05:29 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell