Architect, Applications Engineering

-on experience in FPGA-based prototyping, ASIC design, or SoC validation, with deep understanding of RTL-to-hardware workflows... sales or hardware platform engagements Strong command of FPGA architectures (Xilinx, Intel, or similar), RTL design...

Lugar: Estados Unidos | 27/06/2026 17:06:41 PM | Salario: S/. No Especificado | Empresa: Synopsys

Principal Design Engineer

Work on RTL synthesis and floor planning Build clock trees and perform optimizations Close timing, IR drop and physical... verification Review and Document designs for taping out Interface with Front End RTL design teams and Back End Verification teams...

Lugar: San Jose, CA | 27/06/2026 17:06:56 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

ASIC Physical Design Principal Engineer

differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact RTL-to-GDSII..., identifying efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT...

Lugar: San Jose, CA | 27/06/2026 17:06:00 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Electrical Engineer FPGA - Level 3/4 - Dulles

environment or space application Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis... application Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static...

Lugar: Virginia | 27/06/2026 17:06:28 PM | Salario: S/. $114000 - 171000 per year | Empresa: Northrop Grumman

Lead ASIC DFT (Design-for-Test) Engineer - Remote

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: Estados Unidos | 27/06/2026 17:06:40 PM | Salario: S/. No Especificado | Empresa: Saransh Inc