/SystemVerilog is essential for RTL (Register Transfer Level) design. FPGA Tools: Experience with industry-standard FPGA design...
timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve..., and diagnosis/debug. Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. Review RTL, synthesis, LEC...
developing and deploying methodologies on advanced technology nodes. Strong understanding of complete RTL-to-GDS implementation...
accuracy of SystemC models through comparison with RTL simulations and hardware prototypes, achieving a model fidelity target...
approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design..., and stress scenarios. Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve...
skills across RTL, testbench, and firmware. Knowledge of PCIe/AXI/DDR or similar standard protocols. Experience with Linux... platforms. Port RTL/UVM testbenches from simulation to emulation. Debug SoC/IP level issues in emulation and provide root...
best practices across our verification processes. What You'll Bring: Deep expertise in ASIC IP/ASIC SoC design, RTL, Verilog...
approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design... with RTL designers to resolve issues. Implement and maintain functional coverage, code coverage, assertion coverage...
with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high... simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. Implement...
experience with Fullchip clock mesh and Flex-HTree methods RTL-to-GDSII implementation: Floorplan, Power Grid plan, place... and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow...