Senior FPGA Engineer

, and validate FPGA architectures for high-reliability embedded systems Develop RTL code using VHDL and/or Verilog/SystemVerilog...

Lugar: El Segundo, CA | 07/06/2026 17:06:38 PM | Salario: S/. No Especificado | Empresa: ITResource Hunter

Senior Electrical Engineer- FPGA Development

lifecycle, from concept to production. It takes experts in system architecture definition, RTL design, synthesis, timing.../System Verilog and hardware description language (HDL) coding practices Proficiency in design, register-transfer level (RTL...

Lugar: Round Rock, TX | 07/06/2026 17:06:27 PM | Salario: S/. No Especificado | Empresa: Dell, Inc.

Lead ASIC DFT Engineer

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: Plano, TX | 07/06/2026 17:06:58 PM | Salario: S/. No Especificado | Empresa: Purple Hires Inc