Senior ASIC Physical Design Engineering Technical Lead

experience with Fullchip clock mesh and Flex-HTree methods RTL-to-GDSII implementation: Floorplan, Power Grid plan, place... and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow...

Lugar: San Jose, CA | 27/06/2026 17:06:16 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Digital IC, Account Technology Executive (ATX)

Qualifications: Must have a deep technical knowledge and understanding of the digital design flow from RTL to GDSII including high...-level synthesis, RTL synthesis, static timing analysis, power analysis/optimization, equivalence checking, DFT, digital...

Lugar: San Jose, CA | 27/06/2026 00:06:10 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems