Fpga Design Engineer

development process. From defining requirements and architecture to RTL implementation and system integration, you will play... development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration...

Lugar: Greenville, SC | 04/04/2026 18:04:31 PM | Salario: S/. $120000 - 150000 per year | Empresa: Actalent

ASIC Senior Design Engineer

leadership and mentoring to others. We are looking for a Senior RTL Design Engineer to join our HPE Networking ASIC... and fix timing in RTL to meet the frequency target. · Work with the Verification team to make sure your block is fully...

Lugar: Roseville, CA | 04/04/2026 17:04:45 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise

Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 8+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: Estados Unidos | 04/04/2026 17:04:31 PM | Salario: S/. No Especificado | Empresa: SpaceX

Principal Digital Design Engineer

buffer chips for DDR5, DDR6, and beyond. Job Description Propose, architect, and design RTL in Verilog for use in a mixed... specifications. Fluent in Verilog RTL coding and ASIC design methodology Expertise in digital design implementation, including...

Lugar: Duluth, GA | 04/04/2026 17:04:01 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics