Memory Control Design Engineer

. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible...

Lugar: San Diego, CA | 04/04/2026 17:04:20 PM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 8+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: Estados Unidos | 04/04/2026 17:04:27 PM | Salario: S/. No Especificado | Empresa: SpaceX

Senior FPGA Engineer

expectations Required skills FPGA design experience including thorough design documentation, completion and review of RTL... blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design Ability...

Lugar: Englewood, CO | 04/04/2026 17:04:16 PM | Salario: S/. $130000 - 185000 per year | Empresa: SEAKR Engineering

Data Fabric Verification Engineer

, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design. Coordinate with RTL... with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity...

Lugar: Dallas, GA | 04/04/2026 17:04:21 PM | Salario: S/. $60000 - 148500 per year | Empresa: Wipro

Sr. ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 5+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: Estados Unidos | 04/04/2026 17:04:12 PM | Salario: S/. No Especificado | Empresa: SpaceX