Senior FPGA/DSP Engineer

fixed-point DSP blocks in RTL, such as IIR and FIR filters, PWM generators, delta-sigma modulators, PLLs, DFT/FFT processors...

Lugar: Santa Cruz, CA | 01/04/2026 17:04:45 PM | Salario: S/. $132800 - 199300 per year | Empresa: Joby Aviation

ASIC Design Engineer

documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets.... Crafting micro-architecture, implementing them in RTL, and delivering fully verified, synthesis/timing clean builds...

Lugar: Santa Clara, CA | 01/04/2026 17:04:27 PM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia