Senior FPGA Engineer

expectations Required skills FPGA design experience including thorough design documentation, completion and review of RTL... blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design Ability...

Lugar: Englewood, CO | 09/06/2026 17:06:53 PM | Salario: S/. $130000 - 185000 per year | Empresa: SEAKR Engineering

ASIC Design Engineer

I'm currently hiring for Hardware Engineer opportunity in the Dallas, TX area! This role focuses on front-end RTL... and SystemVerilog blocks for an image and video processing SoC. Work on front-end RTL design, focusing on CPU/GPU-style SoC...

Lugar: Richardson, TX | 09/06/2026 17:06:55 PM | Salario: S/. No Especificado | Empresa: Actalent