Principal/ Sr. Principal FPGA Design Engineer

benches Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static... timing analysis, and power analysis Experience with FPGA simulation tools to verify performance of complex RTL blocks...

Lugar: Rolling Meadows, IL | 05/06/2026 17:06:49 PM | Salario: S/. $119600 - 179400 per year | Empresa: Northrop Grumman

Agentic AI Engineer

, and tool-calling specs that feed Cadence agents the right design context (RTL, scripts, logs, reports, methodology docs) at the... Pipelines. Curate, clean, and label datasets from EDA artifacts (RTL, waveforms, logs, reports, schematics). Build synthetic...

Lugar: Estados Unidos | 05/06/2026 02:06:43 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

ASIC Design Engineer

I'm currently hiring for Hardware Engineer opportunity in the Dallas, TX area! This role focuses on front-end RTL... and SystemVerilog blocks for an image and video processing SoC. Work on front-end RTL design, focusing on CPU/GPU-style SoC...

Lugar: Richardson, TX | 05/06/2026 01:06:49 AM | Salario: S/. No Especificado | Empresa: Actalent