FPGA Verification Engineer (Level 3 or 4)

verification of register transfer level (RTL) code of a complex FPGA at block level and SOC level using VUnit. Development... development and RTL debug Basic Qualifications of Sr. Principal FPGA Verification Engineer: Bachelor’s degree with 8 years...

Lugar: Linthicum, MD | 30/03/2026 17:03:52 PM | Salario: S/. $119600 - 179400 per year | Empresa: Northrop Grumman

Senior React JS Developer

, and CSRF prevention. Write unit and integration tests using Jest, RTL, and Cypress. Mandatory Skills: React JS...

Lugar: Dallas, TX | 30/03/2026 03:03:50 AM | Salario: S/. $60000 - 135000 per year | Empresa: Wipro

Digital/FPGA Engineer Lead - Space

architecture, design, and implementation of FPGA‑based digital systems Develop RTL in Verilog, SystemVerilog, or VHDL for control... Strong experience with Verilog, SystemVerilog, or VHDL Experience across multiple stages of FPGA development: architecture, RTL design...

Lugar: Tempe, AZ | 30/03/2026 02:03:00 AM | Salario: S/. No Especificado | Empresa: Viasat

Design Verification Engineer

. Finds and implements corrective measures to resolve failing tests. Collaborates with CPU architects, RTL developers...++ Experience with RTL development using System verilog Knowledge of system level boot flows and power management. Experience...

Lugar: Austin, TX | 30/03/2026 00:03:53 AM | Salario: S/. $122440 - 172860 per year | Empresa: Intel