FPGA Development Tools Engineer – Synthesis

of FPGA compilation technology. In this role, you will develop and enhance synthesis capabilities that transform RTL designs... strong expertise in RTL design and synthesis, combined with a solid software engineering background and a passion for building scalable...

Lugar: San Jose, CA | 05/06/2026 00:06:53 AM | Salario: S/. No Especificado | Empresa: Altera

Senior FPGA Engineer, LEO Payload FPGA

. - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure... with uArchitecture, RTL coding, FPGA optimization for timing & power, simulation, and validation Preferred Qualifications...

Lugar: Sunnyvale, CA | 04/06/2026 23:06:37 PM | Salario: S/. No Especificado | Empresa: Amazon

Senior Digital Design Engineer

the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. Craft... micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean...

Lugar: Santa Clara, CA | 04/06/2026 20:06:42 PM | Salario: S/. No Especificado | Empresa: Nvidia

Austin Hiring Event - Senior Staff Physical Design Engineer

is available for qualified candidates. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL... tools Work with RTL design teams to drive assembly and design closure. Provide technical direction, coaching...

Lugar: Austin, TX | 04/06/2026 18:06:59 PM | Salario: S/. $132500 - 196140 per year | Empresa: Marvell

Austin Hiring Event - Senior Principal Physical Design Engineer

and infrastructure in alignment with company-wide technology strategy Lead RTL-to-GDSII implementation for multiple SoC programs... technologies used in major foundries Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure...

Lugar: Austin, TX | 04/06/2026 18:06:11 PM | Salario: S/. No Especificado | Empresa: Marvell

ASIC Clocks Design Engineer - New College Grad 2026

Clocking topologies in RTL. Collaborate with Physical design and timing team to evaluate Clocking concerns and develop... solutions for supporting high speed Clocking. Together with other team members, we deliver clock RTL information to GPU, CPU...

Lugar: Santa Clara, CA | 04/06/2026 17:06:26 PM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia