ASIC Engineering Technical Leader- DFT

in San Jose with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams... role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design...

Lugar: San Jose, CA | 04/06/2026 17:06:31 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

CPU Verification Engineer

. In this role, you will collaborate with architects, RTL developers, and physical design teams to verify and validate cutting-edge... measures to resolve test failures Collaborate closely with CPU architects and RTL designers to verify complex architectural...

Lugar: Austin, TX | 04/06/2026 17:06:11 PM | Salario: S/. No Especificado | Empresa: Intel

CPU Performance Research Engineer

and research. Roles and Responsibilities Collaborate with CPU Performance Architecture and RTL team members to identify... architectural performance model Work with RTL and design team to assess implementation cost for new features Collaborate...

Lugar: Santa Clara, CA | 04/06/2026 02:06:35 AM | Salario: S/. No Especificado | Empresa: Qualcomm

Principal Product Engineer

track record of shipping designs or product improvements. ▸ Expert-level understanding of the full RTL-to-GDSII flow... to Have ▸ Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows...

Lugar: San Jose, CA | 04/06/2026 01:06:08 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Senior ASIC AI Engineer

-architecture, RTL, and physical design starting with specification. Using AI agents to process large data and existing codebase..., evaluation frameworks to measure agent accuracy. Experience with System Verilog, RTL and hardware description language...

Lugar: Santa Clara, CA | 04/06/2026 00:06:28 AM | Salario: S/. No Especificado | Empresa: Nvidia

Digital Design Engineer I

principles to support block-level and system-level digital design activities, including RTL development and integration..., computer architecture, or SoC development. Understanding of digital design fundamentals, including RTL design, finite state...

Lugar: Austin, TX | 04/06/2026 00:06:48 AM | Salario: S/. $78750 - 146250 per year | Empresa: Silicon Labs

CPU Architecture Performance Engineer (RISC V)

and compiler technology a plus Collaborate with CPU Performance Architecture and RTL team members to identify opportunities... performance model Work with RTL and design team to assess implementation cost for new features Collaborate...

Lugar: Santa Clara, CA | 04/06/2026 00:06:58 AM | Salario: S/. No Especificado | Empresa: Qualcomm