Staff/ Sr. Staff Design Verification Engineer - QGOV

General Summary: Design Verification Role: Familiarity with RTL design in Verilog and System Verilog Develop... clearance ** Required Qualifications: 5+ years of work experience with RTL/FPGA design (Verilog), embedded system...

Lugar: San Diego, CA | 28/03/2026 22:03:01 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Lead Physical Design Engineer, Amazon Leo

job responsibilities Lead RTL design and development of large subsystems and custom blocks. Integrate IP cores by choosing configuraton.... Support the design through all phases: RTL/Gate simulations, emulation and post silicon implementations. In this role...

Lugar: Austin, TX | 28/03/2026 22:03:59 PM | Salario: S/. No Especificado | Empresa: Amazon

ASIC Digital Backend Physical Implementation Engineer

, and maintain a robust flow from netlist to full closure and GDSII generation. Partner with RTL circuit designers and other layout... and correlation, influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable...

Lugar: Atlanta, GA | 28/03/2026 21:03:43 PM | Salario: S/. $119900 - 191500 per year | Empresa: Ciena

ASIC Digital Design, Senior Staff Engineer

: Define and develop ASIC RTL design and verification at both chip level and block level. Collaborate with cross-functional... teams to design, implement, and verify PCIe interfaces. Perform RTL coding, synthesis, and simulation to ensure design...

Lugar: Austin, TX | 28/03/2026 21:03:16 PM | Salario: S/. No Especificado | Empresa: Synopsys

Senior ASIC Synthesis and STA Engineer

verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages Validate clock... with RTL design principles and hardware description languages Ability to work effectively within multidisciplinary...

Lugar: Atlanta, GA | 28/03/2026 21:03:56 PM | Salario: S/. $119900 - 191500 per year | Empresa: Ciena