Design Verification Engineer

hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading... of architectural, functional, and performance issues. Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet...

Lugar: Santa Clara, CA | 03/06/2026 18:06:17 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Clocking Architect

with RTL, physical design, timing, and verification teams to ensure the clock architecture is correctly modeled and implemented... the full-chip CDC architecture plan: identify, classify, and document every asynchronous clock domain crossing from RTL...

Lugar: San Jose, CA | 03/06/2026 18:06:07 PM | Salario: S/. No Especificado | Empresa: Altera

Senior ICE Emulation Design Engineer

, as well as supporting SW development. Key Responsibilities Partition and synthesize large SOC RTL designs for emulation... with RTL, DV and SW teams to resolve system level bugs Performance optimization Qualifications BS or MS degrees or higher...

Lugar: San Jose, CA | 03/06/2026 17:06:35 PM | Salario: S/. $150000 - 190000 per year | Empresa: Axiado

ASIC Physical Design Technical Lead

experience with Fullchip clock mesh and Flex-HTree methods RTL-to-GDSII implementation: Floorplan, Power Grid plan, place... and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow...

Lugar: San Jose, CA | 03/06/2026 17:06:17 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis...

Lugar: Santa Clara, CA | 03/06/2026 01:06:12 AM | Salario: S/. $110600 - 140000 per year | Empresa: OmniVision

Controls Engineer

in Verilog/VHDL for RTL design, synthesis, and verification PCB layout experience using tools like Altium Designer Experience...

Lugar: Estados Unidos | 03/06/2026 00:06:10 AM | Salario: S/. $130000 - 140000 per year | Empresa: Viridien

Principal Foundry Technologist

in digital design floor planning, STA;taking RTL to GDS and optimize for PPA Some experience in coding using various languages...

Lugar: Redmond, WA | 02/06/2026 23:06:00 PM | Salario: S/. No Especificado | Empresa: Microsoft