Lead ASIC DFT Engineer

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: San Jose, CA | 28/03/2026 20:03:06 PM | Salario: S/. No Especificado | Empresa: Cyient

Digital Circuit Design Engineer

related field, or equivalent practical experience At least 2 years of hands-on experience designing RTL digital logic using...

Lugar: Irvine, CA | 28/03/2026 19:03:22 PM | Salario: S/. $110600 - 140000 per year | Empresa: OmniVision

ASIC Physical Design Engineer

Perform PPA optimization with Fusion compiler to enhance ASIC efficiency. Conduct RTL and netlist level power analysis.... Setup, run, debug, and analyze reports of ASIC flows including Synthesis, PD, Power, and Timing. Implement blocks at RTL...

Lugar: San Francisco, CA | 28/03/2026 18:03:44 PM | Salario: S/. No Especificado | Empresa: Mercor