Senior Engineer, Digital Design Engineering

using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running...

Lugar: Dallas, TX | 29/05/2026 23:05:19 PM | Salario: S/. $123600 - 175440 per year | Empresa: Analog Devices

CPU Physical Design Engineer

of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the... Analysis, Noise analysis, and reliability verification techniques. Strong knowledge of RTL to GDS methodologies and formal...

Lugar: Austin, TX | 29/05/2026 23:05:43 PM | Salario: S/. No Especificado | Empresa: Intel

CPU Physical Design Engineer

of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the... techniques. Knowledge of RTL to GDS methodologies and formal equivalence Experience performing CPU level timing analysis...

Lugar: Austin, TX | 29/05/2026 21:05:15 PM | Salario: S/. No Especificado | Empresa: Intel

Physical Design Engineer

, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso...

Lugar: San Diego, CA | 29/05/2026 21:05:01 PM | Salario: S/. $98500 - 147700 per year | Empresa: Qualcomm

Senior Engineer, Digital Design Engineering

using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running simulations...

Lugar: Somerset, NJ | 29/05/2026 21:05:29 PM | Salario: S/. $127171 - 175440 per year | Empresa: Analog Devices

CPU Physical Design Engineer

of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the... techniques. Knowledge of RTL to GDS methodologies and formal equivalence Experience performing CPU level timing analysis...

Lugar: Austin, TX | 29/05/2026 19:05:58 PM | Salario: S/. $105650 - 172860 per year | Empresa: Intel