Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation... and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area...
Lugar:
Folsom, CA | 29/05/2026 19:05:51 PM | Salario: S/. No Especificado | Empresa:
Intel, RTL design, design verification, firmware, and software teams to ensure our next-generation AI/ML accelerators meet the... networks, ML HW architecture, and/or CI/CD - Familiarity with the validation lifecycle from RTL simulation (SystemVerilog/UVM...
Lugar:
Austin, TX | 29/05/2026 19:05:56 PM | Salario: S/. No Especificado | Empresa:
Amazon responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog...
from RTL to silicon. Throughout the day, you'll balance immediate customer needs-unblocking a team waiting for compute...
Lugar:
Austin, TX | 29/05/2026 17:05:54 PM | Salario: S/. No Especificado | Empresa:
Amazon Booking: Trailer Vendor Ready to Load (RTL) Date, Request System Delivery, Project Schedule, Schedule Customer Meetings...
and architecture definition RTL development (Verilog / SystemVerilog) Digital signal processing theory and implementation High-speed...
and verification. - Proficiency in VHDL/Verilog/SystemVerilog for RTL design and FPGA development. - Hands-on experience with RTL...
. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities... experience in ASIC timing and STA. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge and hands...
Lugar:
San Diego, CA | 29/05/2026 02:05:50 AM | Salario: S/. $115200 - 170390 per year | Empresa:
Marvell and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams... experience in ASIC implementation and synthesis. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge...
Lugar:
San Diego, CA | 29/05/2026 02:05:21 AM | Salario: S/. $115200 - 170390 per year | Empresa:
Marvell. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities... experience in ASIC timing and STA. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge and hands...
Lugar:
San Diego, CA | 29/05/2026 01:05:50 AM | Salario: S/. $160400 - 237320 per year | Empresa:
Marvell