Underwriter II

our full suite of Business Purpose Loans — including Residential Transitional Loans (RTL), DSCR (non-consumer), Bridge, Ground... ideal for someone with a strong background in RTL and DSCR products who thrives in a fast-paced environment...

Lugar: Estados Unidos | 28/05/2026 17:05:50 PM | Salario: S/. No Especificado | Empresa: Park Place Finance, LLC

IP Verification Engineer

who make sure that backbone never breaks. If you've spent several years hunting down the hardest RTL bugs, building... — a world-class, growing semiconductor team that develops, tests, and delivers the functional RTL blocks that go...

Lugar: Austin, TX | 28/05/2026 17:05:26 PM | Salario: S/. No Especificado | Empresa: Ericsson

Principal Engineer, ASIC/VLSI Synthesis and Design

and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams... experience in ASIC implementation and synthesis. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge...

Lugar: San Diego, CA | 28/05/2026 17:05:52 PM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Design Verification Engineer - Fully Remote

. Position: RTL Design Engineers Type: Contract Compensation: $100–$175/hour Location: Remote Duration: 3+ months Commitment... and evaluation. Design and verify RTL components using Verilog/SystemVerilog. Collaborate with architecture, verification...

Lugar: Nueva York, NY | 28/05/2026 17:05:47 PM | Salario: S/. No Especificado | Empresa: Mercor

Principal Digital Design Engineer

buffer chips for DDR5, DDR6, and beyond. Job Description Propose, architect, and design RTL in Verilog for use in a mixed... specifications. Fluent in Verilog RTL coding and ASIC design methodology Expertise in digital design implementation, including...

Lugar: Duluth, GA | 28/05/2026 17:05:02 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams... experience in ASIC implementation and synthesis. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge...

Lugar: San Diego, CA | 28/05/2026 17:05:30 PM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Principal Logic Design Engineer

and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces... and root cause, and provide RTL fix if necessary Provide technical support to FAE team on pre-sales customer engagements...

Lugar: Hillsboro, OR | 28/05/2026 02:05:40 AM | Salario: S/. No Especificado | Empresa: Rambus