Senior ASIC DV Engineer
metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design...
metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design...
has hands-on experience across the full ASIC development cycle — from RTL architecture and design through tapeout, silicon bring... — from RTL architecture and design through tapeout, silicon bring-up, and mass production. KEY RESPONSIBILITIES: Architect...
and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces... and root cause, and provide RTL fix if necessary Provide technical support to FAE team on pre-sales customer engagements...
CPU microarchitect who brings hands-on RTL development experience and a track record of technical leadership. We’re... RTL design of the major functional block. Ownership includes the design definition, implementation and convergence of the...
and power efficient RTL to achieve design targets You will be working with architects, designers, verification and VLSI teams...
, and collaborate with RTL designers, simulation-based verification engineers, and architects to shift verification left and improve..., complexity reduction strategies, and assume-guarantee reasoning Collaborate with RTL designers and architects to define...
cross-domain support for issue resolution to keep project on schedule, at spec and quality (RTL, DV, DFT, PD, emulation, FW...
and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces... and root cause, and provide RTL fix if necessary Provide technical support to FAE team on pre-sales customer engagements...
NVIDIA is seeking elite ASIC Infrastructure engineers to deliver the tooling and environment that enables DV and RTL...
and common detection circuits. Experience with RTL, logic synthesis and verification, knowledge of Place and Route...