Senior ASIC DV Engineer

metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design...

Lugar: San Jose, CA | 21/03/2026 18:03:20 PM | Salario: S/. No Especificado | Empresa: Broadcom

PD/STA Engineer

, and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth... floorplanning Flow and Methodology Development Collaborating with IC Design RTL Engineers Required Skills: TCL/PERL Scripting...

Lugar: San Jose, CA | 21/03/2026 18:03:10 PM | Salario: S/. $16000 - 19000 per year | Empresa: Quest Global

Emulation Engineer

testing. Prior experience with RTL development for Emulation prototypes. Prior experience with C/C++ and TCL...

Lugar: San Jose, CA | 21/03/2026 18:03:27 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Verification Engineer

in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements Help... and hold timing violations with RTL modification. Good written and verbal communication skills. Scripting experience...

Lugar: San Jose, CA | 21/03/2026 18:03:14 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Developer

## Grow with us Senior RTL Design Engineer – Accelerator IP Location: Austin, TX (Hybrid;on-site) Your Next Big... Challenge Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture...

Lugar: Austin, TX | 21/03/2026 18:03:21 PM | Salario: S/. $117000 - 175000 per year | Empresa: Ericsson