Senior Staff EDA Support Engineer
in the Digital domain: Verification, RTL, Constraint, UPF, P&R, and Physical Verification Ability to troubleshoot Soc design...
in the Digital domain: Verification, RTL, Constraint, UPF, P&R, and Physical Verification Ability to troubleshoot Soc design...
circuit simulation (Spectre/ADE), and digital RTL design (SystemVerilog). Nice To Have: Knowledge of mixed mode...
metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design...
, and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth... floorplanning Flow and Methodology Development Collaborating with IC Design RTL Engineers Required Skills: TCL/PERL Scripting...
testing. Prior experience with RTL development for Emulation prototypes. Prior experience with C/C++ and TCL...
in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements Help... and hold timing violations with RTL modification. Good written and verbal communication skills. Scripting experience...
flows, including RTL‑to‑GDSII, verification, and emulation. Proven ability to lead global teams and manage complex...
with compilation, debug, performance testing. Prior experience with RTL development for Emulation prototypes. Prior experience...
automation, and verification. Modelling experience with System Verilog/Real Modelling/Verilog AMS and coding synthesizable RTL...
## Grow with us Senior RTL Design Engineer – Accelerator IP Location: Austin, TX (Hybrid;on-site) Your Next Big... Challenge Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture...