-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design specifications... in high-performance RTL design using Verilog/SystemVerilog. Experience with timing closure, power optimization, and clock...
monthly Store Visit Form for review with RTL and optical team. Ensures all operating policies and procedures are followed...
such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis Experience... in VHDL design for an aerospace environment or space application Proficient in FPGA design flow including items such as RTL...
center silicon. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive..., preferably at advanced technology nodes. Strong expertise in Verilog/System Verilog RTL design for high-performance ASICs...
. Drive Static Timing Analysis (STA) and partner with RTL, physical design, and DFT teams to resolve timing issues across the... design hierarchy. Partner with RTL designers to achieve timing convergence through constraint development and timing-driven...
features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance... and random verification tests Debug test failures to determine the root cause;work with RTL engineers to resolve design defects...
in our next-generation AI processor. You’ll collaborate with experts across architecture, RTL design, physical design, firmware...
:** Premium Retail Services, LLC **Req ID:** 24034 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
:** $17.00 - $18.50 **Company:** Premium Retail Services, LLC **Req ID:** 24054 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
documents. – Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend... with FPGAs (Xilinx, Altera, etc.). – 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. – 3+ years...