ASIC Design Verification Engineer

in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements Help... and hold timing violations with RTL modification. Good written and verbal communication skills. Scripting experience...

Lugar: San Jose, CA | 21/03/2026 18:03:40 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Emulation Engineer

testing. Prior experience with RTL development for Emulation prototypes. Prior experience with C/C++ and TCL...

Lugar: San Jose, CA | 21/03/2026 18:03:08 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

PD/STA Engineer

, and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth... floorplanning Flow and Methodology Development Collaborating with IC Design RTL Engineers Required Skills: TCL/PERL Scripting...

Lugar: San Jose, CA | 21/03/2026 18:03:39 PM | Salario: S/. $16000 - 19000 per year | Empresa: Quest Global

Firmware Development Engineer

. Cross-Functional Collaboration: Partner with RTL and board design engineers to solve challenging cross-domain issues...

Lugar: Santa Clara, CA | 21/03/2026 03:03:12 AM | Salario: S/. No Especificado | Empresa: Intel

Pre-Silicon Verification Engineer

. Finds and implements corrective measures to resolve failing tests. Collaborates with CPU architects, RTL developers... with RTL development Knowledge of system level boot flows and power management. Experience in Computer-Architecture...

Lugar: Austin, TX | 21/03/2026 01:03:52 AM | Salario: S/. No Especificado | Empresa: Intel

New College Grad - Design Engineer, AI

correctness, performance, and efficiency Develop AI‑assisted approaches for design rule interpretation, RTL and architecture... exploration, verification coverage analysis, bug pattern detection, and regression triage Support RTL, gate‑level verification...

Lugar: San Jose, CA | 20/03/2026 23:03:51 PM | Salario: S/. $80000 - 170000 per year | Empresa: Micron