RTL across complex GPU and SoC designs. Working as a mid-to-senior individual contributor, you will serve as a key enabler... standards that align with high-performance and low-power goals. You will own and evolve the RTL flow and build system, including...
Lugar:
Austin, TX | 20/05/2026 17:05:23 PM | Salario: S/. No Especificado | Empresa:
Samsung, and SystemTap / eBPF / perf output Strong understanding of EDA and HPC workload characteristics, including RTL simulation, formal...
digital systems Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions... Strong knowledge of System Verilog and/or VHDL Foundational knowledge of digital logic and timing considerations Experience with RTL...
Lugar:
Tempe, AZ | 20/05/2026 17:05:48 PM | Salario: S/. No Especificado | Empresa:
Viasat of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII implementation flow.... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) Perform hierarchical floor planning...
Bertelsmann, whose other content businesses include the entertainment company RTL Group and the trade book publisher Penguin...
architecture specifications for new features. Support the creation of schematics and/or RTL blocks Define best known design... and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification...
Lugar:
San Jose, CA | 20/05/2026 17:05:12 PM | Salario: S/. $145000 - 246000 per year | Empresa:
Micron level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete... and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence...
Lugar:
Folsom, CA | 20/05/2026 17:05:21 PM | Salario: S/. No Especificado | Empresa:
Intel tools Required Qualifications Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design...
, spanning RTL-to-GDS, signoff, debug, and regression Build and maintain data pipelines to extract, normalize, and analyze...
, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect... IPs. In this role, you will own and drive DFT/DFx architecture definition, RTL implementation, methodology development...