SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis...

Lugar: Santa Clara, CA | 14/05/2026 20:05:18 PM | Salario: S/. $110600 - 140000 per year | Empresa: OmniVision

Senior Staff Design Engineer - Memory Subsystem COE

customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.... What You Can Expect Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration...

Lugar: Santa Clara, CA | 14/05/2026 18:05:23 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

Verification Engineer

behavioral models and validate designs by comparing them against RTL implementations Analyze simulation results, debug failures... Strong expertise in RTL verification methodologies, including System Verilog Experience with ASIC verification flows and design...

Lugar: San Jose, CA | 14/05/2026 18:05:41 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Eng Sr - Elec

is expected to perform activities including assisting in design architecture, ownership of RTL coding, synthesis, place and route...

Lugar: Nashua, NH | 14/05/2026 18:05:39 PM | Salario: S/. No Especificado | Empresa: BAE Systems