Senior Engineer, Digital Design Engineering

using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running...

Lugar: Wilmington, MA | 13/05/2026 23:05:44 PM | Salario: S/. $124342 - 175440 per year | Empresa: Analog Devices

Senior Logic Design Engineer

of a section of FPGA/CPLD development, focusing on micro-architectural definition, RTL coding, logic debug, synthesis, and timing... and targets. Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic review, bring-up...

Lugar: Santa Clara, CA | 13/05/2026 23:05:32 PM | Salario: S/. No Especificado | Empresa: Nvidia

Senior Engineer, Digital Design Engineering

and integration of designs. Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary... to this section): Demonstrated expertise (DE) applying digital design methodologies, including RTL design, Lint, and CDC, to design...

Lugar: Colorado | 13/05/2026 22:05:21 PM | Salario: S/. $112020 - 166668 per year | Empresa: Analog Devices

Senior Engineer, Digital Design Engineering

using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running simulations...

Lugar: Beaverton, OR | 13/05/2026 19:05:40 PM | Salario: S/. $121680 - 174440 per year | Empresa: Analog Devices

FPGA Engineer

for control and dataflow applications in small satellite avionics. Develop and verify VHDL RTL and top-level block diagram...

Lugar: State College, PA | 13/05/2026 17:05:41 PM | Salario: S/. No Especificado | Empresa: Airbus