Principal Engineer, GPU Design Verification (Subsystems)
, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven...
, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven...
. Conducts Physical Inventory twice per year. Completes monthly Store Visit Form for review with RTL and optical team. Ensures...
baseband and subsystem designs. You will collaborate closely with system, firmware, and RTL design teams to ensure first‑time... with simulation acceleration, formal verification, and HW/SW co‑verification Strong OOP programming skills and/or RTL design...
using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running...
of a section of FPGA/CPLD development, focusing on micro-architectural definition, RTL coding, logic debug, synthesis, and timing... and targets. Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic review, bring-up...
domains including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs...
and integration of designs. Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary... to this section): Demonstrated expertise (DE) applying digital design methodologies, including RTL design, Lint, and CDC, to design...
using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running simulations...
of chip design and verification flows including RTL simulation, emulation, FPGA prototyping, and virtual platforms Ability...
for control and dataflow applications in small satellite avionics. Develop and verify VHDL RTL and top-level block diagram...