Memory Design Engineer | HBM - TPG
, including scripting experience (Python, TCL, Perl). Prior register‑transfer level (RTL) design flow experience in DRAM...
, including scripting experience (Python, TCL, Perl). Prior register‑transfer level (RTL) design flow experience in DRAM...
from RTL to GDSII. Contribute to the development, improvement, and automation of various power analysis flows. This includes..., providing actionable feedback to the RTL design team. Responsibilities: Perform comprehensive power analysis at various...
with RTL simulators and emulators, hardware (HW-in-the-loop), and detailed performance models. Bring up system...
comprehensive power analysis at various design stages, spanning from RTL to GDSII. Contribute to the development, improvement... processes. Investigate and address power inefficiencies, providing actionable feedback to the RTL design team. Minimum...
with general HW concepts, Verilog RTL coding and simulations/debug, GPU and SOC Architectures, and Machine Learning/Deep Learning...
/Formal Verification required from RTL to tapeout with industry-standard tools. Understanding of hardware architecture... and hands-on skills in RTL/logic design for timing closure. Experience in clock-domain-crossing checking, MTBF analysis...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...
customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation...
and performance requirements. (Verilog/SystemVerilog). Complete high-quality, area-optimal, low-power RTL design using industry..., RTL coding, FPGA, Computer Architecture, Digital Verification. Minimum 3 years of experience in similar role of Digital...
). Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design... understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis. Advanced Node...