FPGA Power Management Engineer

, bridging architecture, RTL, firmware, and lab validation. This is a hands-on position with real impact on production silicon... across abstraction levels—from power-performance modeling and architecture simulation to RTL, firmware integration, and lab bring-up...

Lugar: San Jose, CA | 01/05/2026 18:05:24 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Senior ASIC Physical Design Technical Lead

planning RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity.... Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology...

Lugar: San Jose, CA | 01/05/2026 17:05:37 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Sr Principal Digital Design Engineer

-architecture and RTL for complex power management integrated circuits. Work closely with system and chip architects to design...-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans...

Lugar: San Diego, CA | 01/05/2026 02:05:40 AM | Salario: S/. No Especificado | Empresa: Marvell

Principal STA Engineer

-functional teams-RTL designers, physical design specialists, and SI/PI engineers-to drive timing convergence and ensure robust... is composed of experts in physical design, RTL architecture, SI/PI analysis, and verification, working collaboratively to achieve...

Lugar: Austin, TX | 01/05/2026 02:05:33 AM | Salario: S/. No Especificado | Empresa: Synopsys

Design Verification (DV) Engineer

flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers... Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage...

Lugar: Estados Unidos | 01/05/2026 02:05:32 AM | Salario: S/. $175000 - 250000 per year | Empresa: Hudson River Trading

Staff Manager - SoC Design

7+ years or more of RTL experience 1 + years of experience managing a design team Demonstrated ability to lead...

Lugar: San Diego, CA | 01/05/2026 01:05:22 AM | Salario: S/. $145400 - 215340 per year | Empresa: Marvell

Sr Staff Digital Design Engineer

Expect Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated... full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing...

Lugar: San Diego, CA | 01/05/2026 01:05:11 AM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Staff Physical Design Engineer

with company-wide technology strategy Perform RTL-to-GDSII implementation for multiple SoC programs, including synthesis... design flow, RTL integration, synthesis, and timing closure highly preferred Strong knowledge of modern EDA tools and flows...

Lugar: Irvine, CA | 01/05/2026 00:05:13 AM | Salario: S/. $112300 - 166280 per year | Empresa: Marvell