Senior ASIC Timing Engineer
with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create...
with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create...
-architecture and RTL for complex power management integrated circuits. Work closely with system and chip architects to design...-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans...
FPGA design experience, including Xilinx Vivado Strong knowledge of System Verilog Experience with RTL design for various...
specifications and define micro-architecture of the design Implement designs using low-power RTL coding techniques Collaborate.... To be successful in this role you will need the following skills: Fluent in SystemVerilog RTL coding techniques. Experience in high speed...
that gives the team confidence in the RTL before silicon is committed. This is a full-ownership DV role. You will write the DV...-cause issues to RTL or testbench, and track bug closure through the design team. Post-Silicon Support: Provide debug...
10+ years or more of RTL experience 3 + years of experience managing a design team Demonstrated ability to lead...
product expansion through robust internationalization (i18n), including right-to-left (RTL) support, while helping scale... internationalization (i18n) best practices, including RTL layout support and localization workflows Collaborate with backend and platform...
at Astranis. If you have not yet graduated from a four-year university, please apply to be an Intern. Role RTL Development... including high speed data converters, memories, MCUs Write software to interface and test RTL in hardware Collaborate closely...
of progress metrics. What We're Looking For BS degree or higher in EE or CE or CS 12-15+ years or more of RTL...
. Serve as a primary coordination point between floorplan and partner teams including architecture, RTL, PD, DFT, package...