Digital ASIC Design Engineer for Mixed-Signal IPs

General Summary: The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the... flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor...

Lugar: San Diego, CA | 10/04/2026 00:04:30 AM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

FPGA Engineer

with RTL simulation tools (Questasim) Familiarity with advanced FPGA platforms (MPSoC, RFSoC, Ultrascale+, Versal, Stratix...

Lugar: Tewksbury, MA | 09/04/2026 17:04:11 PM | Salario: S/. $80000 - 190000 per year | Empresa: FishEye Software

Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 10+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: Estados Unidos | 08/04/2026 17:04:40 PM | Salario: S/. No Especificado | Empresa: SpaceX