Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 8+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: Estados Unidos | 04/04/2026 17:04:03 PM | Salario: S/. No Especificado | Empresa: SpaceX

Control Room - Associate

to assist in the implementation, and enforcement of the firm's information-barrier, MNPI, and Restricted Trading List (RTL... the administration and oversight of the firm's Restricted Trading List (RTL), including adding, monitoring, and removing...

Lugar: Salt Lake City, UT | 03/04/2026 23:04:11 PM | Salario: S/. $70000 - 85000 per year | Empresa: iCapital

Emulation Lead Engineer

and resolution of hardware, software, and model issues. Develop HW/SW enablement flows and tools to accelerate RTL validation...

Lugar: Santa Clara, CA | 03/04/2026 22:04:24 PM | Salario: S/. No Especificado | Empresa: Marvell

Senior SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 03/04/2026 18:04:35 PM | Salario: S/. No Especificado | Empresa: TikTok

SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 03/04/2026 17:04:24 PM | Salario: S/. No Especificado | Empresa: TikTok

ASIC Design Engineer (Onsite)

-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design... from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes...

Lugar: San Jose, CA | 03/04/2026 17:04:35 PM | Salario: S/. No Especificado | Empresa: Cisco Systems