validation. Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA... → Synthesis → STA → Physical Design → Tape-out Experience writing and debugging SDC timing constraints, including multi-cycle...
Description Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation... engineering, computer engineering, or equivalent - Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC...
margins, guard-bands, and sign-off criteria for advanced node designs. Managing complexities at 7nm, 5nm, and 3nm nodes..., including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution. Developing and reviewing SDC constraints...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Collaborate...
and Vivado Experience coding, simulating, testing, and debugging HDL designs Proven work with clock domain crossing (CDC...), and multi‑clock designs Experience with high‑speed serial interfaces (e.g., 8b/10b, LVDS, SERDES‑style logic) Embedded...
. Your Impact Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs... in Electrical Engineering or Computer Engineering +1 years of ASIC experience. Experience developing block-level and full-chip SDC...
and Vivado Experience coding, simulating, testing, and debugging HDL designs Proven work with clock domain crossing (CDC...), and multi-clock designs Experience with high-speed serial interfaces (e.g., 8b/10b, LVDS, SERDES-style logic) Embedded...
integration. Driving creation of reusable assets (templates, checklists, reference designs) and coordinating IRAD projects.... Understanding of PLD implementation details: device constraints (XDC/SDC), timing closure, board-level bring-up, and hardware-in-the...
Description Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create... experience - Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints - Experience with automation...
for Construction. Drive the Project SDC/CA phase from time of construction kick off (construction by others) through final redline... reps to ensure designs are compliant and our team is operating in a safe environment. Participate in creation of process...