, and collaborator to build, manage, and lead the Commissioning (Cx) responsibilities required on Steam Data Centers (SDC) deployments... qualified testing firms to provide the Cx and quality services per the SDC standards. Responsible for the completion...
, and collaborator to build, manage, and lead the Commissioning (Cx) responsibilities required on Steam Data Centers (SDC) deployments... qualified testing firms to provide the Cx and quality services per the SDC standards. Responsible for the completion...
About the Role We’re looking for a highly organized, enthusiastic, and motivated individual to join our team as an Entry-Level Account Executive. In this role, you will support the Sales team in managing retail accounts, preparing product...
Job Overview: We are looking for a proactive and organized Returns and Repairs Coordinator to join our team at a leading diamond jewelry company. The ideal candidate will be responsible for managing returns, overseeing the repair process, ...
validation. Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA... → Synthesis → STA → Physical Design → Tape-out Experience writing and debugging SDC timing constraints, including multi-cycle...
Description Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation... engineering, computer engineering, or equivalent - Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC...
margins, guard-bands, and sign-off criteria for advanced node designs. Managing complexities at 7nm, 5nm, and 3nm nodes..., including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution. Developing and reviewing SDC constraints...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Collaborate...
and Vivado Experience coding, simulating, testing, and debugging HDL designs Proven work with clock domain crossing (CDC...), and multi‑clock designs Experience with high‑speed serial interfaces (e.g., 8b/10b, LVDS, SERDES‑style logic) Embedded...
. Your Impact Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs... in Electrical Engineering or Computer Engineering +1 years of ASIC experience. Experience developing block-level and full-chip SDC...