Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration..., on-chip variation, signal integrity, and power-aware timing. Proven ability to develop and manage complex hierarchical SDC...
to develop and own complex SDC timing constraints for large hierarchical system-on-chip designs with multiple clock domains..., and voltage and temperature conditions. Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC...
ever. You will drive physical implementation of advanced high‑bandwidth memory (HBM) system‑on‑chip (SoC) logic and base die designs..., clocking concepts, and Synopsys Design Constraints (SDC). Working knowledge of power intent methodologies including Unified...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...
across complex AMD SoC designs, ensuring correctness across use cases and configurations Build and maintain automation... flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (e.g., Lint, CDC, RDC, LEC, VCLP/CLP...
margins, guard-bands, and sign-off criteria for advanced node designs. Managing complexities at 7nm, 5nm, and 3nm nodes..., including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution. Developing and reviewing SDC constraints...
with hardware engineers on FPGA/SoC PCB board designs. Experience writing timing constraints (SDC) to achieve timing closure... on high-speed FPGA designs. Familiarity with common communication protocols (SPI, I2C, AXI, Avalon, Ethernet, AMBA, Wishbone...
). Ability to collaborate with hardware engineers on FPGA/SoC PCB board designs. Experience writing timing constraints (SDC...) to achieve timing closure on high-speed FPGA designs. Familiarity with common communication protocols (SPI, I2C, AXI, Avalon...
, including development of automation and scripts to support these flows · Develop timing constraints (SDC) ensuring correctness... · Ensure designs meet timing, power, and integration requirements prior to tapeout · Support final integration, signoff...
and implementation of next-generation STA algorithms addressing multi-billion-cell designs, advanced timing effects, and non-linear..., and complex architectural challenges. Diagnosing systemic issues involving SDC interpretation, timing convergence, path pessimism...