. Assists in investigating design/manufacturing factors such as equipment or part availability, manufacturability, ease... in Space Vehicle (SV) Test Operations including the test development process, test execution, data analysis, anomaly resolution...
, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse... verificaiton environment involving processors, high speed peripheral(PCIe,UCIe,DDR) Work with cross functional(PD,DFT,Design...
-power design. Exposure to formal verification or SV/UVM-based design verification. Start Date Week of 04/23.... Position: RTL Design Engineers Type: Contract Compensation: $100–$175/hour Location: Remote Duration: 3+ months Commitment...
Engineer with deep Space Vehicle Assembly Integration and Test (SV AI&T) experience in Chantilly, VA to support a very dynamic... Government points of contact (GPOCs) relative to ongoing SV AI&T activities happening across diverse geographically located...
to integration activities, and driving architecture improvements throughout the SV and mission lifecycle. This position will work... challenges, interface exchanges, and resolution of SV issues. Collaborate closely with the Phoenix team to onboard SVs into the...
-D. Responsibilities and duties include, but are not limited to System Design Responsibilities Provides technical expertise... standards, system protection, design engineering, DCC Operations, telecom and other key teammates. Interfacing with external...
, and end-to-end flow analysis Develop operational view (OV), technical standards view (TV), and systems & services view (SV... Persona capabilities Design and develop comprehensive Service-Oriented Architecture (SOA) solutions Conduct and approve end...
-speed IO, SoC interconnect, low-power design Exposure to formal verification or SV/UVM-based design verification Track 2...Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing...
-speed IO, SoC interconnect, low-power design Exposure to formal verification or SV/UVM-based design verification Track 2...Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing...
-speed IO, SoC interconnect, low-power design Exposure to formal verification or SV/UVM-based design verification Track 2...Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing...